Master 1 in computer science (M1 SIF)

Ecole Normale Supérieur of Rennes (ENS Rennes)

Licence 3 in computer science (L3 SIF)

Ecole Normale Supérieur of Rennes (ENS Rennes)

• CS : Computer architecture, C/network, C++, OCaml/lambda-calculus, logic, Turing machines, Distributed Algorithms
• Mathematics : Optimisation, Finite fields, probability and statistics, …
• Other : English, teaching methodology, …

First year in computer science engineering school

Ecole Nationale Supérieure d’Informatique et de Mathématiques Appliqués de Grenoble (ENSIMAG), Grenoble

• CS : Computer architecture (writing RISC-V 32bit VHDL processor, RISC-V assembly), Python, C, Network, Cybersecurity, Operational Research, …
• Mathematics : Lebesgue Integral, Fourrier Transform, Information Theory, Probabilities, Statistics, Digital analysis, …
• Other : English, German, Economy, environmental transition, …

CPGE MP2I/MPI*

Lycée Descartes, Tours

Maths, Computer science, physics, english

Research project (TIPE) : Hex game ; theorical considerations, algorithm playing and solving it

Baccalauréat général

Lycée Montesquieu, Le Mans

Obtained in 2022 with high honours (Mention Très Bien)

• Specialities : Mathematics, Physics and Computer Science
• English and German as second/third languages
• Options : expert mathematics, ancient greek and cinema

Research project during Master 1

PACAP @ INRIA Rennes, 1 day / week during the whole year

Subject: improving in-Order performances through speculation with HW/SW codesign
Supervisor: Simon Rokicki

Abstract: we want to add on a small in-Order CPU branch, value and memory-dependency prediction/speculation. However, we want to be able to control it thanks to a modified ISA, in order to improve the physical complexity/costs, while trying to keep or improve good performances. In a first time, we did focus on branch prediction, and especially specifying different branch predictors for different branching.

Summer research Internship

TARAN @ INRIA Rennes, 11 weeks

Subject: study origin of differences between in-Order and Out-of-Order CPU and implement in High-Level-Synthsis a superscalar RISC-V in-Order processor
Supervisor: Simon Rokicki

Abstract: during this internship, I studied the origin of differences in performances between in-Order CPU and Out-of-Order ones (cf. McFarlin’s article), by learning a lot about in-Order and VLIW CPUs and the techniques used with them (speculation on in-Order machines, such as ld.as on Itanium, software pipelining, …). Next to this, I started implementing an in-Order CPU that would incorporate these ideas in the future, by modifying Comet, a High-Level-Synthesis CPU written in C++ to make it superscalar.

Check internship report or slides.

Engineer assistant internship in laboratory

MADMAX @ TIMA (INRIA Grenoble), 10 weeks

Subject: track down the origin of differences of RISC-V manycore cache simulators
Supervisor: Julie Dumas

Abstract : QEMU and gem5 are two great computer architecture for different reasons (fidelity of simulation for gem5, speed of simulation, especially for manycore systems for QEMU). Recently, QEMU got a plugin system allowing it to easily run cache simulation on top of it. However, these two simulators give different results on the same benchmarks, which is the problematic of this internship.

Check blog post, internship report or slides.

NumWorks calculator (Epsilon, Omega)

Contributed to Epsilon, official firmware of the NumWorks calculator, and helped creating a fork called Omega targetting power users.
Written firstly as a monolithic C/C++ bare metal firmware, it changed with time to a really simple bootloader/kernel/userland division to allow third party application in userland without being able to control the exam LED.
Including a home-made Computer Algebra System (poincare) with tokenizer/lexer/AST simplification and micropython.

TODO : blog post ?